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January 2007
HYS64D32301[G/H]U-5-B HYS[64/72]D64xxx[G/H]U-[5/6]-B HYS[64/72]D128xxx[G/H]U-[5/6]-B
184-Pin Unbuffered Double-Data-Rate Memory Modules UDIMM DDR SDRAM
Internet Data Sheet
Rev. 1.22
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D32301[G/H]U-5-B, HYS[64/72]D64xxx[G/H]U-[5/6]-B, HYS[64/72]D128xxx[G/H]U-[5/6]-B Revision History: 2007-01, Rev. 1.22 Page All 23 Subjects (major changes since last revision) Adapted internet edition
tDQSS min from 0.75ns to 0.72ns tRFC min from 70ns to 65ns
Qimonda update Added new product type Added raw card C Diagram Updated IDD values Added SPD Code for new product type
Previous Revision: 2006-09, Rev. 1.21 All 4 16 18 20 Previous Revision: 1.2
Previous Revision: Rev. 1.1
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-CXBY-V2JX
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
1
1.1
Overview
Features
* * * * * * * * Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM JEDEC standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. Standard reference layout Gold plated contacts DDR400 speed grade supported Lead-free
This chapter contains features and the description.
* 184-Pin Unbuffered Double-Data-Rate Memory Modules (ECC and non-parity) for PC and Workstation main memory applications * One rank 32M x 64, 64M x 64, 64M x72 and two ranks 128M x 64, 128M x72 organization * standard Double Data Rate Synchronous DRAMs Single +2.5V ( 0.2V) power supply * Built with 512-Mbit in P-TSOPII-66 package * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
TABLE 1
Performance for -5 and -6
Part Number Speed Code Speed Grade Max. Clock Frequency Component Module @CL3 @CL2.5 @CL2 -5 DDR400B PC3200 - 3033 -6 DDR333B PC2700 - 2533 166 166 133 Unit -- -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The Qimonda HYS64D32301[G/H]U-5-B, HYS[64/72]D64xxx[G/H]U- [5/6]-B and HYS[64/72]D128xxx[G/H]U-[5/6]-B are industry standard 184-Pin Unbuffered Double-Data-Rate Memory Modules (UDIMM) organized as 32M x 64M (256 MB), 64M x64 (512 MB), 128M x64 (1 GB) for non-parity and 64M x72 (512 MB), 128M x72 (1 GB) for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
TABLE 2
Ordering Information
Type PC3200 (CL=3.0) HYS64D64300GU-5-B HYS72D64300GU-5-B HYS64D128320GU-5-B HYS72D128320GU-5-B PC2700 (CL=2.5) HYS64D64300GU-6-B HYS72D64300GU-6-B HYS64D128320GU-6-B HYS72D128320GU-6-B PC3200 (CL=3.0) HYS64D32301HU-5-B HYS64D64300HU-5-B HYS72D64300HU-5-B HYS64D128320HU-5-B HYS72D128320HU-5-B PC2700 (CL=2.5) HYS64D64300HU-6-B HYS72D64300HU-6-B HYS64D128320HU-6-B HYS72D128320HU-6-B PC2700U-25330-A0 PC2700U-25330-A0 PC2700U-25330-B0 PC2700U-25330-B0 one rank 512 MB DIMM one rank 512 MB ECC-DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) PC3200U-30330-C0 PC3200U-30330-A0 PC3200U-30330-A0 PC3200U-30330-B0 PC3200U-30330-B0 one rank 256 MB DIMM one rank 512 MB DIMM one rank 512 MB ECC-DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) PC2700U-25330-A0 PC2700U-25330-A0 PC2700U-25330-B0 PC2700U-25330-B0 one rank 512 MB DIMM one rank 512 MB ECC-DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) PC3200U-30330-A0 PC3200U-30330-A0 PC3200U-30330-B0 PC3200U-30330-B0 one rank 512 MB DIMM one rank 512 MB ECC-DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) Compliance Code Description SDRAM Technology
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "20330" means CAS latency of 2.0 clocks, RCD (Row-Column-Delay) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
2
Pin Configuration
and Table 5 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Unbuffered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4
TABLE 3
Pin Configuration of UDIMM
Pin# Name Pin Type I NC I I I NC I I I I NC I I NC I I I Buffer Type SSTL - SSTL SSTL SSTL - SSTL SSTL SSTL SSTL - SSTL SSTL - SSTL SSTL SSTL Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Chip Select Rank 0 Chip Select Rank 1 Note: 2-rank module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Complement Clock Signals 2:0 Function
Clock Signals 137 16 76 138 17 75 21 111 CK0 NC CK1 CK2 CK0 NC CK1 CK2 CKE0 CKE1 NC Control Signals 157 158 S0 S1 NC 154 65 63 RAS CAS WE Clock Signals 2:0
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin#
Name
Pin Type I I I I I I I I I I I I I I I I NC I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL -
Function
Address Signals 59 52 48 43 41 130 37 32 125 29 122 27 141 118 115 BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 NC 167 A13 NC Bank Address Bus 2:0 Address Bus 11:0
Address Bus 11:0
Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin#
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 Data Bus 63:0
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Pin# 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44
Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 NC
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL - SSTL - SSTL - SSTL -
Function Data Bus 63:0
Check Bit 0 Note: ECC type module Note: Non-ECC module Check Bit 1 Note: ECC type module Note: Non-ECC module Check Bit 2 Note: ECC type module Note: Non-ECC module Check Bit 3 Note: ECC type module Note: Non-ECC module Check Bit 4 Note: ECC type module Note: Non-ECC module
45
CB1 NC
49
CB2 NC
51
CB3 NC
134
CB4 NC
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Pin# 135
Name CB5 NC
Pin Type I/O NC I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I I I I I I I I I NC I I/O I I I AI PWR
Buffer Type SSTL - SSTL - SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - CMOS OD CMOS CMOS CMOS - -
Function Check Bit 5 Note: ECC type module Note: Non-ECC module Check Bit 6 Note: ECC type module Note: Non-ECC module Check Bit 7 Note: ECC type module Note: Non-ECC module Data Strobe Bus 7:0
142
CB6 NC
144
CB7 NC
5 14 25 36 56 67 78 86 47
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC
Data Strobe 8 Note: ECC type module Note: Non-ECC module Data Mask Bus 7:0
97 107 119 129 149 159 169 177 140
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 NC
Data Mask 8 Note: ECC type module Note: Non-ECC module Serial Bus Clock Serial Bus Data Slave Address Select Bus 2:0
EEPROM 92 91 181 182 183 1 184 SCL SDA SA0 SA1 SA2
Power Supplies
VREF VDDSPD
I/O Reference Voltage EEPROM Power Supply
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Pin# 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176
Name
Pin Type PWR
Buffer Type -
Function I/O Driver Power Supply
VDDQ
VDD
PWRzp
-
Power Supply
VSS
GND
-
Ground Plane
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin# Other Pins 82 9, 10, 71, 90, 101, 102, 103, 113, 163, 173
Name
Pin Type O NC
Buffer Type OD -
Function
VDDID
NC
VDD Identification
Not connected
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TABLE 4
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
TABLE 6
Address Format
Density 256 MB 512 MB 512 MB 1 GB 1 GB Organization 32M x64 64M x64 64M x72 128M x64 128M x72 Memory Ranks 1 1 1 2 2 SDRAMs 32M x16 64M x8 64M x8 64M x8 64M x8 # of SDRAMs 4 8 8 16 18 # of row/bank/ columns bits 13/2/9 13/2/11 13/2/11 13/2/12 13/2/12 Refresh 8K 8K 8K 8K 8K Period 64 ms 64 ms 64 ms 64 ms 64 ms Interval 7.8 ms 7.8 ms 7.8 ms 7.8 ms 7.8 ms
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
FIGURE 1
Pin Configuration 184-Pin, UDIMM
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3
3.1
Electrical Characteristics
Operating Conditions
This chapter lists the electrical characteristics.
This chapter describes the operating conditions.
TABLE 7
Absolute Maximum Ratings
Parameter Symbol min. Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current Values typ. -- -- -- -- -- -- 1 50 max. Unit Note/ Test Condition -- -- -- -- -- -- -- --
VIN, VOUT VIN VDD VDDQ TA TSTG
PD
-0.5 -1 -1 -1 0 -55 -- --
VDDQ + 0.5
+3.6 +3.6 +3.6 +70 +150 -- --
V V V V C C W mA
IOUT
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
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TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage EEPROM supply voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Values Typ. 2.5 2.6 2.5 2.6 2.5 -- 0.5 x VDDQ -- -- -- -- -- -- -- Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x VDDQ V V V V V V V V V V V V -- A Unit Note1) / Test Condition
VDD VDD VDDQ VDDQ VDDSPD VSS, VSSQ VREF VTT
2.3 2.5 2.3 2.5 2.3 0 0.49 x VDDQ
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4) 5)
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71 -2
VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6
1.4 2
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
CK Inputs Input Differential Voltage, CK VID(DC) and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current
8) 8) 8)
8)6)
VIRatio II
7)
Any input 0 V VIN VDD; All other pins not under test = 0 V
8)9)
Output Leakage Current
IOZ
-5 -- 16.2
-- -- --
5 -16.2 --
A mA mA
DQs are disabled; 0 V VOUT
Output High Current, Normal IOH Strength Driver Output Low Current, Normal Strength Driver 1) 0 C TA 70 C
2) 3) 4) 5) 6) 7)
VDDQ 8) VOUT = 1.95 V 8) VOUT = 0.35 V 8)
IOL
8) 9)
DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Inputs are not recognized as valid until VREF stabilizes. Values are shown per component
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TABLE 9
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol -5 DDR400B Min. DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time Max. +0.5 +0.6 0.55 0.55 8 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.40 +0.50 -- -- -- -- -- 0.60 -- -- -- -6 DDR333 Min. -0.7 -0.6 0.45 0.45 -- 7.5 7.5 0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- -- Max. +0.7 +0.6 0.55 0.55 -- 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.45 +0.55 -- -- -- -- -- 0.60 -- -- -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit
Note1) / Test Condition
tAC tDQSCK tCH tCL tHP tCK
-0.5 -0.6 0.45 0.45 5 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns ns
Min. (tCL, tCH)
Min. (tCL, tCH)
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input)
tDH tDS tIPW
0.4 0.4 2.2 1.75 -0.7 -0.7 0.75 -- --
DQ and DM input pulse width (each input) tDIPW Data-out high-impedance time from CK/CK tHZ Data-out low-impedance time from CK/CK tLZ Write command to 1 DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle)
st
2)3)4)5)6) 2)3)4)5)7) 2)3)4)5)7) 2)3)4)5)
tDQSS tDQSQ tQHS tQH tDQSL,H tDSS
tCK
ns ns ns
TSOPII 2)3)4)5) TSOPII 2)3)4)5)
2)3)4)5) 2)3)4)5)
tHP -tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.7
tHP -tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.8
tCK tCK tCK tCK
ns
2)3)4)5)
DQS falling edge hold time from CK (write tDSH cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time
2)3)4)5)
tMRD tWPRES tWPST tWPRE tIS
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
ns ns
Fast slew rate
3)4)5)6)10)
Slow slew rate
3)4)5)6)10)
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Parameter
Symbol
-5 DDR400B Min. Max. -- -- 1.1 0.60 70E+3 -- -- -- -- -- -- -- -- -- --
-6 DDR333 Min. 0.75 0.8 0.9 0.40 42 60 72 18 18 12 15 -- 1 75 200 Max. -- -- 1.1 0.60 70E+3 -- -- -- -- -- -- -- -- -- --
Unit
Note1) / Test Condition
Address and control input hold time
tIH
0.6 0.7
ns ns
Fast slew rate
3)4)5)6)10)
Slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay
tRPRE tRPST tRAS tRC tRFC
0.9 0.40 40 55 70 15 15 10 15 -- 2 75 200
tCK tCK
ns ns ns ns ns ns ns ns
2)3)4)5)
tRCD Precharge command period tRP Active to Autoprecharge delay tRAP Active bank A to Active bank B command tRRD Write recovery time tWR Auto precharge write recovery + precharge tDAL
time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11)
tRCD - tRASmin
tCK tCK
ns
2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns, slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
2)3)4)5)12) Average Periodic Refresh Interval -- 7.8 -- 7.8 s 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400)
tWTR tXSNR tXSRD tREFI
2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK
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3.2
Current Conditions and Specification
This chapter describes the Conditions and Specification.
TABLE 10
IDD Specification for HYS[64/72]D[32/64/128]3xxHU-5-B
HYS64D128320HU-5-B HYS64D128320GU-5-B HYS64D64300HU-5-B HYS64D64300GU-5-B HYS72D64300HU-5-B HYS72D64300GU-5-B HYS64D32301HU-5-B Product Type HYS72D128320HU-5-B Unit Note 1)2)
Organization
256 MB x64 1 Rank -5
512 MB x64 1 Rank -5 Max. 480 560 20 140 100 60 200 580 600 980 20.8 1360 Typ. 640 720 10 240 150 100 310 680 720 1640 22 2080 Max. 800 880 30 290 210 130 380 800 840 1960 42 2480
512 MB x64 1 Rank -5 Typ. 720 810 20 270 170 110 350 770 810 1850 30 2340 Max. 900 990 40 320 230 140 420 900 950 2210 50 2790
1 GB x64 2 Ranks -5 Typ. 950 1030 30 480 300 190 620 990 1030 1950 45 2390 Max. 1180 1260 64 580 420 260 750 1180 1220 2340 80 2860
1 GB x72 2 Ranks -5 Typ. 1070 1160 31 540 340 220 700 1120 1160 2200 50 2690 Max. 1330 1420 70 650 470 290 850 1320 1370 2630 90 3210 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 3) 3)4)
Symbol
Typ. 400 460 10 120 80 50 170 480 500 820 11 1140
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx [component] + n x IDD3N [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the component IDDx data sheet values as: (m + n) x IDDx [component]
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
TABLE 11
IDD Specification for HYS[64/72]D[64/128]3xxHU-6-B
HYS64D128320HU-6-B HYS64D128320GU-6-B HYS64D64300HU-6-B HYS64D64300GU-6-B HYS72D64300HU-6-B HYS72D64300GU-6-B Product Type HYS72D128320HU-6-B Unit Note 1)2)
Organization
512 MB x64 1 Rank -6
512 MB x72 1 Rank -6 Max. 720 800 30 240 190 120 330 720 760 1760 42 2230 Typ. 680 770 10 230 150 100 320 690 730 1670 24 2110 Max. 810 900 40 270 220 140 370 810 860 1980 47 2510
1 GB x64 2 Ranks -6 Typ. 880 960 30 400 270 180 560 900 930 1760 43 2150 Max. 1050 1130 64 480 380 240 660 1050 1090 2090 80 2560
1 GB x72 2 Ranks -6 Typ. 990 1080 290 450 310 200 630 1010 1040 1980 49 2420 Max. 1180 1270 70 540 430 270 740 1180 1220 2350 94 2880 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 3) 3)4)
Symbol
Typ. 600 680 10 200 140 90 280 620 650 1480 22 1870
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx [component] + n x IDD3N [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx [component]
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * * * * Table 12 "HYS[64/72]D[64/128]3x0GU-5-B" on Page 20 Table 13 "HYS[64/72]D[64/128]3x0GU-6-B" on Page 24 Table 14 "HYS[64/72]D[32/64/128]3xxHU-5-B" on Page 28 Table 15 "HYS[64/72]D[64/128]3x0HU-6-B" on Page 32
TABLE 12
HYS[64/72]D[64/128]3x0GU-5-B
HYS64D128320GU-5-B HYS64D64300GU-5-B HYS72D64300GU-5-B Product Type HYS72D128320GU-5-B 1 GByte x72 PC3200U- 30330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 50 50 02
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC3200U- 30330 Rev. 0.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02
1 GByte x64
2 Ranks (x8) 2 Ranks (x8) PC3200U- 30330 Rev. 0.0 HEX 80 08 07 0D 0B 02 40 00 04 50 50 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
2 2
PC3200U- 30330 Rev. 0.0 HEX 80 08 07 0D 0B 01 40 00 04 50 50 00
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320GU-5-B
HYS64D64300GU-5-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC3200U- 30330 Rev. 0.0 HEX 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37
HYS72D64300GU-5-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC3200U- 30330 Rev. 0.0 HEX 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 PC3200U- 30330 Rev. 0.0 HEX 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37
Label Code JEDEC SPD Revision Byte# 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 Description Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
PC3200U- 30330 Rev. 0.0 HEX 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK@ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
Not used
tRCmin [ns]
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320GU-5-B
HYS64D64300GU-5-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC3200U- 30330 Rev. 0.0 HEX 41 28 28 50 00 00 00 00 50 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30
HYS72D64300GU-5-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC3200U- 30330 Rev. 0.0 HEX 41 28 28 50 00 00 00 00 3F 7F 7F 7F 7F 7F 51 00 00 xx 36 34 44 31 32 38 33 32 PC3200U- 30330 Rev. 0.0 HEX 41 28 28 50 00 00 00 00 51 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32
Label Code JEDEC SPD Revision Byte# 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Description
PC3200U- 30330 Rev. 0.0 HEX 41 28 28 50 00 00 00 00 3E 7F 7F 7F 7F 7F 51 00 00 xx 36 34 44 36 34 33 30 30
tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
Not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8
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Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320GU-5-B
HYS64D64300GU-5-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC3200U- 30330 Rev. 0.0 HEX 47 55 35 42 20 20 20 20 20 20 1x xx xx xx xx 00
HYS72D64300GU-5-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC3200U- 30330 Rev. 0.0 HEX 30 47 55 35 42 20 20 20 20 20 1x xx xx xx xx 00 PC3200U- 30330 Rev. 0.0 HEX 30 47 55 35 42 20 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200U- 30330 Rev. 0.0 HEX 47 55 35 42 20 20 20 20 20 20 1x xx xx xx xx 00
99 - 127 Not used
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
TABLE 13
HYS[64/72]D[64/128]3x0GU-6-B
HYS64D128320GU-6-B HYS64D64300GU-6-B HYS72D64300GU-6-B Product Type HYS72D128320GU-6-B 1 GByte x72 PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1
1 GByte x64
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320GU-6-B
HYS64D64300GU-6-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 54 7F 7F
HYS72D64300GU-6-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 43 7F 7F PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 55 7F 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 Description
PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 42 7F 7F
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax-1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
Not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
Not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2)
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HYS72D128320GU-6-B
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320GU-6-B
HYS64D64300GU-6-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 47 55 36 42 20 20 20 20 20 20 1x
HYS72D64300GU-6-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 36 34 44 31 32 38 33 32 30 47 55 36 42 20 20 20 20 20 1x PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 47 55 36 42 20 20 20 20 20 1x
Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code
PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 36 34 44 36 34 33 30 30 47 55 36 42 20 20 20 20 20 20 1x
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Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320GU-6-B
HYS64D64300GU-6-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00
HYS72D64300GU-6-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00 PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00
99 - 127 Not used
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
TABLE 14
HYS[64/72]D[32/64/128]3xxHU-5-B
HYS64D128320HU-5-B HYS64D32301HU-5-B HYS64D64300HU-5-B HYS72D64300HU-5-B Product Type HYS72D128320HU-5-B 1 GByte x72 2 Ranks (x8) Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1
Organization
256MB x64 1 Rank (x16)
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8)
1 GByte x64 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC3200U PC3200U PC3200U PC3200U PC3200U -30331 -30330 -30330 -30330 -30330 Rev. 1.0 HEX 80 08 07 0D 0A 01 40 00 04 50 50 00 82 10 00 01 0E 04 1C 01 02 20 C1 Rev. 0.0 HEX 80 08 07 0D 0B 01 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 Rev. 0.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 Rev. 0.0 HEX 80 08 07 0D 0B 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320HU-5-B
HYS64D32301HU-5-B
HYS64D64300HU-5-B
Organization
256MB x64 1 Rank (x16)
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8)
HYS72D64300HU-5-B
Product Type
1 GByte x64 2 Ranks (x8)
1 GByte x72 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 Description
PC3200U PC3200U PC3200U PC3200U PC3200U -30331 -30330 -30330 -30330 -30330 Rev. 1.0 HEX 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 16 7F Rev. 0.0 HEX 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 3E 7F Rev. 0.0 HEX 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 50 7F Rev. 0.0 HEX 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 3F 7F Rev. 0.0 HEX 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 51 7F
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
Not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
Not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1)
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HYS72D128320HU-5-B
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320HU-5-B
HYS64D32301HU-5-B
HYS64D64300HU-5-B
Organization
256MB x64 1 Rank (x16)
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8)
HYS72D64300HU-5-B
Product Type
1 GByte x64 2 Ranks (x8)
1 GByte x72 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Description Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17
PC3200U PC3200U PC3200U PC3200U PC3200U -30331 -30330 -30330 -30330 -30330 Rev. 1.0 HEX 7F 7F 7F 7F 51 00 00 xx 36 34 44 33 32 33 30 31 48 55 35 42 20 20 20 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 36 34 44 36 34 33 30 30 48 55 35 42 20 20 20 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 55 35 42 20 20 20 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 36 34 44 31 32 38 33 32 30 48 55 35 42 20 20 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 48 55 35 42 20 20 20 20
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HYS72D128320HU-5-B
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320HU-5-B
HYS64D32301HU-5-B
HYS64D64300HU-5-B
Organization
256MB x64 1 Rank (x16)
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8)
HYS72D64300HU-5-B
Product Type
1 GByte x64 2 Ranks (x8)
1 GByte x72 2 Ranks (x8)
Label Code JEDEC SPD Revision Byte# 90 91 92 93 94 95 - 98 Description Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200U PC3200U PC3200U PC3200U PC3200U -30331 -30330 -30330 -30330 -30330 Rev. 1.0 HEX 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 1x xx xx xx xx 00
99 - 127 Not used
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HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
TABLE 15
HYS[64/72]D[64/128]3x0HU-6-B
HYS64D128320HU-6-B HYS64D64300HU-6-B HYS72D64300HU-6-B Product Type HYS72D128320HU-6-B 1 GByte x72 PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1
1 GByte x64
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC2700U- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
32
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320HU-6-B
HYS64D64300HU-6-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 54 7F 7F
HYS72D64300HU-6-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 43 7F 7F PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 55 7F 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 Description
PC2700U- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 42 7F 7F
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
Not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
Not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2)
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
33
HYS72D128320HU-6-B
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320HU-6-B
HYS64D64300HU-6-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 55 36 42 20 20 20 20 20 20 1x
HYS72D64300HU-6-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 36 34 44 31 32 38 33 32 30 48 55 36 42 20 20 20 20 20 1x PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 48 55 36 42 20 20 20 20 20 1x
Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code
PC2700U- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 36 34 44 36 34 33 30 30 48 55 36 42 20 20 20 20 20 20 1x
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
34
HYS72D128320HU-6-B
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
HYS64D128320HU-6-B
HYS64D64300HU-6-B
Organization
512MB x64 1 Rank (x8)
512MB x72 1 Rank (x8) PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00
HYS72D64300HU-6-B
Product Type
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00 PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700U- 25330 Rev. 0.0 HEX xx xx xx xx 00
99 - 127 Not used
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
35
HYS72D128320HU-6-B
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
5
Package Outlines
FIGURE 2
Raw Card C DDR UDIMM HYS64D32301HU-5-B (1 Rank Module)
This chapter contains the package outlines of the products.
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
36
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
FIGURE 3
Raw Card A DDR UDIMM HYS64D64300HU-[5/6/7]-B (1 Rank Module)
0.1 A B C
133.35 128.95 2.7 MAX. A 0.15 A B C
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
37
17.8
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
FIGURE 4
Raw Card A DDR UDIMM HYS72D64300HU-[5/6/7F]-B (1 Rank Module)
133.35 128.95 2.7 MAX.
1)
0.1 A B C
0.15 A B C
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
38
17.8
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
FIGURE 5
Raw Card B DDR UDIMM HYS64D128320HU-[5/6/7]-B (2 Ranks Module)
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
39
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
FIGURE 6
Raw Card B DDR UDIMM HYS72D128320HU-[5/6/7]-B (2 Rank Module)
0.1 A B C
133.35 128.95 4 MAX.
1)
0.15 A B C
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
40
17.8
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Table of Contents
1 1.1 1.2 2 3 3.1 3.2 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Rev. 1.22, 2007-01 03292006-CXBY-V2JX
41
Internet Data Sheet
Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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